The successful implementation of high-k metal-gate (HKMG) in the 45 nm technology node has made it a necessary step in the key process flow for the sub-30 nm technology node. Intel, who has committed to a high-k metal-gate-last approach, is now the leader in mass production of 45 nm and 32 nm chips. And former IBM alliances such as Samsung, TSMC and Infineon have recently switched from the high-k gate-first approach to the gate-last approach.
In the gate last approach, after high temperature ion-implant anneal, the polycrystalline silicon dummy gate should be removed and then a metal gate electrode is formed by a filling process, as shown in FIG. 1. An insulating layer 2, polycrystalline silicon dummy gates 3, gate sidewalls 4, and interlayer dielectric layer (ILD) 5 are sequentially formed on substrate 1, as shown in FIG. 1A. The polycrystalline silicon dummy gates 3 are removed to form gate openings trench 6, and a metal gate electrode material is then filled, as shown in FIG. 1B. The polycrystalline silicon gate sidewalls 4 is a spacer made of a material of silicon oxide or silicon nitride, and the insulating layer 2 below the polycrystalline silicon gates is formed of deposited high-k material, or the material of silicon oxide or silicon oxynitride. At present, three technologies exist for removing the polycrystalline silicon dummy gates. They are dry etching, wet chemical etching and dry-wet mixed etching. The wet chemical etching and dry-wet etching processes have become the popular methods in the related experiments and reports.
After removing the polycrystalline silicon dummy gates 3, an effective monitoring method is required to determine whether the polycrystalline silicon has been thoroughly removed. Because polycrystalline silicon residual will have a big negative impact on the device performance. The process is a complex process for 32 nm and even smaller technology node. How to effectively monitor the removal of the polycrystalline silicon dummy gates 3 has not been reported in the prior art. The most direct method is to see the cross section using scanning electron microscope after removing the dummy gates 3. But such a method is a destructive method, and feedback is often slow, so this method cannot be directly used to effectively monitor dummy gate removal process, especially in the mass production process. Optical detection means is readily used in the IC industry to monitor the module process. With the technology nodes further scaling down, device structure and film stack composed of thinner films have become more complex. The traditional optical detection methods are not able to quickly and accurately monitor the fine trench structure after dummy gate removal. Therefore, a direct, quick, accurate, and non-damaging monitor method for dummy gate removal process is needed in order to determine whether the polycrystalline silicon is thoroughly removed or not.